1. Field of the Invention
The present invention relates to a comparator circuit.
2. Description of Related Art
FIG. 8 shows a configuration of the comparator circuit, shown by Patent Document 1 (Japanese Patent Application Laid Open No. Hei 5-249148). As shown in FIG. 8, a comparator circuit 1 includes PMOS transistors Tr1 and Tr3, and NMOS transistors Tr2 and Tr4.
The PMOS transistor Tr1 and the NMOS transistor Tr2 are connected in series between terminals 5 and 7. The PMOS transistor Tr1 and the NMOS transistor Tr2 are connected to each other at a common node 10, and further, their respective gates are connected to the common node 10.
The PMOS transistor Tr3 and the NMOS transistor Tr4 are connected in series between the terminal 5 and a terminal 6. The PMOS transistor Tr3 and the NMOS transistor Tr4 are connected to each other by using a terminal 9 as a common node. The respective gates of the PMOS transistor Tr3 and the NMOS transistor Tr4 are connected to the common node 10.
The terminals 5 and 6 are applied with a potential VDD as an operating voltage and a ground voltage GND, respectively. A target voltage Ue to be detected is inputted across the terminals 7 and 6. The terminal 9 serves as an output terminal of the comparator circuit 1 to output an output voltage signal Ua.
However, the comparator circuit 1 poses problems as given below. First, the comparator circuit 1 is vulnerable to temperature variations and fabrication variations. This is due to the fact that, in order to set a fixed operating threshold of the comparator circuit 1 for Ue>0, the operating threshold is selected so that the NMOS transistors Tr2 and Tr4 may have different transfer characteristic curves. The MOS transistor in an input stage does not have high breakdown voltage characteristics because of a circuit configuration.
FIG. 9 illustrates a circuit configuration addressing these problems and disclosed in Patent Document 2 (Japanese Patent Application Laid Open No. Hei 9-46191). As shown in FIG. 9, a comparator circuit 2 includes PMOS transistors Tr1 and Tr3, and NMOS transistors Tr2 and Tr4. The PMOS transistor Tr1 and the NMOS transistor Tr2 are connected in series between terminals 5 and 7. The PMOS transistor Tr1 and the NMOS transistor Tr2 are connected to each other at a common node 10, and further, their respective gates are connected to the common node 10.
The PMOS transistor Tr3 and the NMOS transistor Tr4 are connected in series between the terminal 5 and a terminal 8. The PMOS transistor Tr3 and the NMOS transistor Tr4 are connected to each other by using a terminal 9 as a common node. The respective gates of the PMOS transistor Tr3 and the NMOS transistor Tr4 are connected to the common node 10.
The terminal 5 is applied with a positive potential VD of an operating voltage, and a terminal 6 is applied with a standard voltage GND. The terminal 8 is applied with a reference voltage VR. The reference voltage VR acts as a voltage to determine a switching threshold of the comparator circuit 1. A target voltage Ue to be detected is inputted across the terminals 7 and 6. The terminal 9 serves as an output terminal of the comparator circuit 2 to output an output voltage signal Ua.